Welcome to the Capacitor Fundamentals Series, where we teach you about the ins and outs of chips capacitors – their properties, product classifications, test standards, and use cases – in order to help you make informed decisions about the right capacitors for your specific applications. After describing visual standards for chip capacitors in our previous article, let’s discuss chip attachment and termination guidelines.
Traditionally, leaded capacitors were used in high volume printed circuit boards (PCBs), such that the components were assembled or “stuffed” into plated through holes on P.C. boards. Nowadays multilayer ceramic capacitors (MLCCs) are often sold as chip (or leadless) components that can be surface mounted to high-density boards using high speed automation. However, variables affecting attachment of chips to substrates are of increasing importance. The inherent mismatch of thermal and physical properties of the components to the substrates and solders is intensified by the use of chip components directly bonded to the substrate material. In this article, we discuss different chip capacitor attachment methods, thermal properties, and performance specifications to consider.
Chip bonding to substrates can be categorized into two general classes: 1) methods involving solder and 2) those involving other bonds, such as epoxies and wire bonds (thermal-compression and ultrasonic bonding).
Solder attachment can be accomplished in a variety of ways:
A common method used in the surface mount industry is the solder paste reflow technique, and involves the following basic steps:
The advent of high component density circuits, which utilize surface mount technology, has resulted in the need for more thermal efficient and reliable soldering methods. Surface mount components are attached to the substrate by pick and place machines, and held in place by epoxy or solder paste for subsequent processing, which may involve any of the following:
The objective of any solder attachment system is the same: to attain clean and smooth solder joints with no bridging or open areas and without physical defects. Not all these parameters are solder processing dependent, since certain defects can be attributed to component or circuit faults or selection of materials. The degree of bond strength of the components to the board is also dependent on the quality of the chip termination, its own intrinsic strength, solderability, and resistance to solder leach, as well as the selection of solder.
Nonconductive thermosetting epoxies are utilized to affix the capacitor body to the substrate, in preparation for secondary electrical connection, either by soldering (solder reflow or solder wave) or by wire bonding (ultrasonic or thermal-compression bonding). An electrical mechanical bond, analogous to soldering of chips, can be achieved by using conductive epoxies, which contain metal powders of silver, copper or aluminum. Epoxies require a low temperature cure in the range of 25°C to 150°C.
Wire bonding methods involve welding of very thin gold or aluminum wires to components to effect an electrical connection; physical attachment of the capacitor body to the substrate must be made by other means, such as epoxy bonding. The wire bond to the chip metallization or substrate pad is attained with heat and pressure, applied to the fine diameter wire tip. Localized heat at the bond is applied from an external source, as in thermal-compression bonding or ultrasonic bonding. In both cases, the heat and pressure result in intermetallic mingling of the wire and host material, effecting a bond.
Chip attachment methods invariably involve thermal cycling of the component. The expansion characteristics of the chip and substrate and the mechanical properties of the bonding medium result in residual stresses that affect the reliability of the bonded chip.
Chip capacitors can tolerate relatively high temperatures, by virtue of their processing, which typically involves a 1100°C to 1200°C firing of the dielectric body, followed with a second firing of the end metallization at approximately 850°C. Chips therefore could be cycled to as high as 850°C with no detrimental effect on the devices, provided the process does not expose the product to sudden or nonuniform temperature changes, which can cause thermal shock failure. Capacitors with nickel barrier terminations, which have a solder coat over the nickel, (or solder coated terminations) are restricted to the reflow temperature of the solder.
Temperature cycling causes a change in the mean interatomic spacing of the atoms in the crystal lattice, due to variations in thermal energy. The characteristic dimensional change of materials with temperature is a function of temperature, and if the dimensional changes caused by temperature cycling are not uniform, the resultant differential strains cause stresses within the material. These stresses are significant in ceramic materials, which, unlike metals, lack ductility to relieve the stress. Heating of a material causes a positive expansion, resulting in compressive stress. Conversely, cooling results in tensile forces as the material attempts to contract. As ceramics are characteristically weaker under tensile load, it follows that the type of temperature change, i.e. heating or cooling, as well as the rate, uniformity and degree of change are critical. Thermal cycling of chip capacitors therefore involves the following general precautions:
The effects of capacitor geometry are self-evident; thermal gradients and resultant stresses are directly proportional to chip mass; hence, larger units are more susceptible to thermal shock than smaller devices. Also, the contribution of preferential heat conduction of end terminations to undesirable stresses increases with larger or longer chips, as more mass is available to maintain the thermal gradients.
Without mechanical restriction, thermally induced stresses are released once the capacitor attains a steady state condition, at any given temperature. Capacitors bonded to substrates, however, will retain some stress, due primarily to the mismatch of expansion of the component to the substrate. The residual stress on the chip is also influenced by the ductility and hence the ability of the bonding medium to relieve the stress. Unfortunately, the thermal expansions of chip capacitors differ significantly from those of substrate materials.
Chips bonded to alumina therefore will retain a tensile stress, as the expansion coefficient of the dielectric material exceeds that of the substrate. On cooling, the chip capacitor will attempt to shrink more than the substrate but is restrained from doing so by the substrate material and solder or epoxy bond. Chips bonded to PCB will retain a compressive stress, as the substrate material attempts to shrink more than the chip. In either case, a shear stress is incorporated into the bond medium; the reliability of the bond therefore is greatly dependent on the load bearing capability of the bonding material.
Solders are the most common bonding alloys used in capacitor attachment. “Low temperature” solders (with flow points under 250°C) are generally tin-lead alloys, with or without silver additions. “High temperature” solders (with flow points of 260°C to 370°C) are based on high lead content alloyed with silver and/or tin or based on gold alloyed with germanium or tin.
Solders are selected based on the assembly temperature restrictions of the circuit, the hardness or ductility of the alloy, and the comparability of the solder to the chip termination and substrate conductor composition. Common solder types, flow points and hardness are tabulated in Table 1.
Table 1. Common bonding alloys
Of importance are the following considerations:
At the solder flow temperature, tin-lead alloys absorb silver (or gold) from the chip termination and/or the substrate pad. This effect is minimized by using solders which contain some percentage of silver and by limiting the time at reflow temperature to the minimum required to obtain good wetting and a well-rounded fillet. Excursion of temperature above the flow point of the solder also need to be avoided, as the leaching rate increases rapidly with temperature. The leaching effect is cumulative; repeated reflow of the solder during processing of the circuit will aggravate the problem.
Capacitor termination alloys and geometry are designed to reduce the leaching effects of solders. Termination materials have evolved from pure silver to silver-palladium alloys, typically 80Ag-20Pd, as the palladium inhibits silver leaching. Leaching, if it occurs, is predominant at the corners and edges of the chip termination, where the termination alloy is thinnest. This effect is minimized by the chip manufacturer by rounding of the corners and edges of the chip with a tumbling process before terminations are applied to obtain a more uniform thickness of coverage.
Vapor phase reflow and dual wave soldering, utilized with surface mount technology, have imposed solder leach requirements on components which preclude the use of silver-palladium terminations. Best resistance to solder heat is attained by the use of barrier type terminations, which have a nickel layer plated over a silver termination, with a solder or tin protective overcoat to enhance solderability and prevent oxidation of the base metal layer. Capacitors with such terminations will survive molten solder at 260°C with no discernible leaching effect for several minutes versus less than twenty seconds for the best Pd-Ag alloys (since nickel is relatively insoluble in Sn, Pb or Ag and therefore acts as a barrier to solder leaching).
As described previously, thermal expansion mismatch of the chip capacitor and the substrate material results in residual shear stress at the bond. Theoretical calculations indicate that this stress can exceed 7000 psi, sufficient to lead to rupture of the chip (if the latter is under tension) or failure of the bond (if the chip is under compression). Fortunately, this condition is alleviated by the ability of the bonding alloy to deform and absorb the majority of the stress. The ductility of the solder alloys is inversely proportional to the hardness of the material; hence, use of softer solders (of lower Brinell hardness) is desirable.
The most common solder used in hybrid circuit application is Sn62 (62Sn,36Pb,2Ag). Selection of other solders is often predicated on the need for higher temperature tolerance of the circuit, i.e., bonding alloys with higher flow points are mandatory.
Capacitor terminations consist of metal-frit (glass) compounds, which are fused to the capacitor body to effect an electrical connection between the internal capacitor electrodes and the circuit pads. Terminations can be classified into two general categories: 1) older thick film silver or silver-palladium (80Ag-20Pd) metallizations and 2) the more popular barrier type termination used for surface mount components.
The silver-palladium termination has adequate resistance to solder leach and less tendency to tarnish than pure silver terminations. Silver finds application mostly on units destined for axial or radial leading or on specialty items, such as high voltage capacitors which require the use of more ductile silver metal to reduce thermal shock hazards to these units when leaded.
Silver bearing terminations can tarnish. Usually packed with a tarnish retardant paper, capacitors will store indefinitely and solder properly with the appropriate fluxes. Severely tarnished units can be restored to a clean metal finish by refiring of the product to approximately 700°C to 800°C. Note that product supplied in reeled format cannot be effectively protected by tarnish retardant paper, as units stored in bulk; hence, inventory planning or the use of barrier termination is recommended.
Barrier layer terminations are based on plating technology to provide 100 to 150 microinches of nickel thickness over a fired silver termination. As nickel readily oxidizes, a second tin/solder or tin layer of 200 to 250 microinches thick is plated over the nickel to protect it and provide a readily solderable surface with good shelf life.
The electrolytic process is perhaps the preferred method of nickel deposition. A current is utilized to deposit nickel from nickel sulfamate and nickel chloride in a boric acid solution onto the silver termination of the capacitor. This termination differs from conventional materials in that the frit which bonds the termination to the capacitor must be chemically resistant to the plating solutions and thus is bismuth free. (Such frits do not promote solderability; hence, units with this termination are unsolderable unless properly plated with nickel and solder.) Immediately after the nickel process, units must undergo the solder process before the onset of any oxidation of the base metal layer. Units are electroplated using tin and lead concentrates in a deionized water solution.
An electroless method of nickel deposition, based on chemical reduction of nickel boron solutions and catalytic activators, can also provide a continuous nickel barrier layer, but this is not as suitable for tin lead plating. Alternate application of a solder coat by wave soldering methods creates dimensional tolerance difficulties, which is not desirable for components to be taped and reeled for use in surface mount technology
The distinct advantage of the nickel barrier termination is evident in its name; it serves not only as a guard against solder leach, by virtue of the relatively insoluble nature of nickel in solder alloys, but also forms a barrier to the formation of intermetallic compounds in the solder joint which can adversely affect the long term reliability of the bond. Non-barrier terminations can be affected by a time-dependent diffusion phenomenon of Ag, Pd and Sn atoms, which accelerate with thermal cycling and can eventually lead to stress cracks separating the component from the assembly. Capacitors with nickel barrier terminations have been shown to arrest the diffusion process and the formation of intermetallic compounds, hence maintaining the integrity of the bond. Although it is a characteristic of all nickel deposition to retain a contractile or tensile condition, the industry has developed the methods to plate the material with controlled metallographic structure and ductility to produce physical and mechanical properties suitable for all the dielectric types of multilayer capacitors.
Chip terminations and bonding alloys contain metals (notably silver and tin), which can hydrolyze in the presence of water moisture. Under the influence of an electric field, the hydroxide can dissociate to form metal cations, which have a net positive charge and can migrate to the cathode. This phenomenon occurs with AC voltage as well as with a DC bias, and the severity is directly proportional to the voltage gradient. Given enough time, a bridge of silver or tin will form between chip terminations, reducing the insulation resistance and eventually forming an electrical short. Avoidance of this problem can be accomplished with the use of very expensive gold terminations and substrate conductors or with the elimination of water moisture from the circuit, which precludes the formation of mobile cations. The latter is accomplished by hermetic sealing of circuits or the use of waterproof encapsulants such as epoxies.
Hopefully, Part 13 gave you a better understanding of soldering and chip termination guidelines and how these best practices may affect your specific application. In Part 14, we’ll be diving into useful formulas and calculations for capacitors. Also, check out our Knowles Precision Devices Capacitors to view our complete product offering.
To learn more about capacitors, download our ebook, A Guide to Selecting the Right Capacitor for Your Specific Application.