---
title: "Build-to-Print Basics Part 8: Conductors"
description: Build-to-Print Basics Part 8 provides basic and multilayer conductor guidelines as well as information on fine line conductor features.
image: https://blog.knowlescapacitors.com/hubfs/Buld%20to%20Print%208%20Conductors.png
---

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## Knowles Precision Devices Blog

# Build-to-Print Basics Part 8: Conductors

Posted by [Tim Bice](https://blog.knowlescapacitors.com/blog/author/tim-bice) on Jan 27, 2021 9:00:00 AM

![Tim Bice](https://blog.knowlescapacitors.com/hubfs/Tim%20Bice.jpeg)

- [Tweet](https://twitter.com/share)

To provide a better understanding of build-to-print in general and the breadth of our offerings, as well as how our thin-film technology can benefit your applications, we’ve put together a [Build-to-Print Basics series](https://info.knowlescapacitors.com/build-to-print-basics). Part 8 provides basic and multilayer conductor guidelines as well as information on fine line conductor features.

![Buld to Print 8 Conductors](https://blog.knowlescapacitors.com/hs-fs/hubfs/Buld%20to%20Print%208%20Conductors.png?width=1200&name=Buld%20to%20Print%208%20Conductors.png)

 

In our overview of metallization in [part 6](https://blog.knowlescapacitors.com/blog/build-to-print-series-part-6-metallization) we touched on the conductor layer as one of the four layers in a standard metallization system. Now it’s time to take a more in-depth look at this layer. In general, the conductor layer for all circuit designs contains critical dimensions necessary for compliance and performance. It is important to consider these dimensions as outlined in Tables 1 and 2 below when designing thin-film circuits both to achieve appropriate functionality and to not add unnecessary cost to the design.  

#### Basic Conductor Standard Layout Guidelines

| **Feature** | **Values and Tolerances\*** | **Comments** |
| --- | --- | --- |
| ![Build-to-Print eBook Graphics_d1a-1](https://blog.knowlescapacitors.com/hs-fs/hubfs/Build-to-Print%20eBook%20Graphics_d1a-1.png?width=300&name=Build-to-Print%20eBook%20Graphics_d1a-1.png) | .003" | Per side 20 percent minimum taper |
| ![Build-to-Print eBook Graphics_d1-2](https://blog.knowlescapacitors.com/hs-fs/hubfs/Build-to-Print%20eBook%20Graphics_d1-2.png?width=300&name=Build-to-Print%20eBook%20Graphics_d1-2.png) | .005" | Per side 20 percent minimum taper |
| ![Build-to-Print eBook Graphics_d3-1](https://blog.knowlescapacitors.com/hs-fs/hubfs/Build-to-Print%20eBook%20Graphics_d3-1.png?width=300&name=Build-to-Print%20eBook%20Graphics_d3-1.png) | .0004 minimum ± .0001" | Minimum space widths and minimum line widths are a function of conductor thickness |
| ![Build-to-Print eBook Graphics_d4-2](https://blog.knowlescapacitors.com/hs-fs/hubfs/Build-to-Print%20eBook%20Graphics_d4-2.png?width=300&name=Build-to-Print%20eBook%20Graphics_d4-2.png) | .001" minimum | .003" preferred |
| ![Build-to-Print eBook Graphics_d5-1](https://blog.knowlescapacitors.com/hs-fs/hubfs/Build-to-Print%20eBook%20Graphics_d5-1.png?width=300&name=Build-to-Print%20eBook%20Graphics_d5-1.png) | .007" ± .005" | .006" typical radius, length 2x material thickness |
| ![Build-to-Print eBook Graphics_d6-1](https://blog.knowlescapacitors.com/hs-fs/hubfs/Build-to-Print%20eBook%20Graphics_d6-1.png?width=300&name=Build-to-Print%20eBook%20Graphics_d6-1.png) | .005" minimum +25%/-50% | Increase or decrease of design area |
| ![Build-to-Print eBook Graphics_d7-1](https://blog.knowlescapacitors.com/hs-fs/hubfs/Build-to-Print%20eBook%20Graphics_d7-1.png?width=300&name=Build-to-Print%20eBook%20Graphics_d7-1.png) | ± .003" | ± .001" by request |
| ![Build-to-Print eBook Graphics_d8-1](https://blog.knowlescapacitors.com/hs-fs/hubfs/Build-to-Print%20eBook%20Graphics_d8-1.png?width=300&name=Build-to-Print%20eBook%20Graphics_d8-1.png) | 0 - .003" |   |

\*Conductor tolerances of <0.001" will require more costly tooling to ensure compliance.

#### Multilayer Conductor Standard Layout Guidelines

| **Feature** | **Values and Tolerances** | **Comments** |
| --- | --- | --- |
| ![Build-to-Print eBook Graphics_d9-1](https://blog.knowlescapacitors.com/hs-fs/hubfs/Build-to-Print%20eBook%20Graphics_d9-1.png?width=300&name=Build-to-Print%20eBook%20Graphics_d9-1.png) | .003" Diameter | Ground signal ground up to 2 levels |
| ![Build-to-Print eBook Graphics_d10-2](https://blog.knowlescapacitors.com/hs-fs/hubfs/Build-to-Print%20eBook%20Graphics_d10-2.png?width=300&name=Build-to-Print%20eBook%20Graphics_d10-2.png) | .002" width .004" pitch | Ground signal ground up to 2 levels |
| ![Build-to-Print eBook Graphics_d11](https://blog.knowlescapacitors.com/hs-fs/hubfs/Build-to-Print%20eBook%20Graphics_d11.png?width=300&name=Build-to-Print%20eBook%20Graphics_d11.png) | .005" |   |

#### Fine Line Conductor Features

Devices such as filters, diplexers, Lange couplers, directional couplers, interdigitated capacitors, and spiral inductors rely on the precision of conductor line width and line spacing to achieve targeted performance. As a result, there are a number of features that will vary depending on the line widths used in the conductor layer with various materials (Table 3).

#### Minimum Line Width and Conductor Spacing Tolerance

First, the characteristic impedance of transmission lines is governed by line widths. Next, the coupling between transmission lines and the control of the even and odd mode impedance to implement couplers and filters is governed by the line widths and the spacing between the adjacent transmission lines.

Additionally, the precise control of the spacing between the coupled lines ensures uniformity in voltage standing wave radio (VSWR) and coupling necessary to make coupler and filter performance repeatable. Edge acuity is also dependent on the thickness of the metal layers required, but generally is less than 0.1 mil. By selecting the proper [substrate](https://blog.knowlescapacitors.com/blog/build-to-print-basics-part-5-substrate-selection)/[metallization](https://blog.knowlescapacitors.com/blog/build-to-print-series-part-6-metallization) system, excellent edge acuity can be achieved and finished line widths will be within ±0.1 mils of the design dimension.

Finally, fine line width and line space geometries are impacted by the quality of the ceramic surface. Some materials used in thin-film products have grain structures and surface imperfections that may cause the loss of control of fine line widths and line space geometries. While polishing can be used to improve the quality of the surface, this technique is also somewhat limited since some materials do not hold up well to the forces created during polishing. However, one material that is not as limited is polished alumina. The surface quality is high and 1 mil line width/spacing is possible and repeatable when vias are present while 0.75 mil line width/spacing is possible and repeatable when vias are not used.

In [the next post](https://blog.knowlescapacitors.com/blog/build-to-print-basics-part-9-vias) we will take a more in-depth look at vias. In the meantime, you can check out the rest of our [Build-to-Print Basics series posts](https://info.knowlescapacitors.com/build-to-print-basics) to learn more about our build-to-print and thin film offerings or [download the comprehensive Build-to-Pring Ebook.](https://info.knowlescapacitors.com/build-to-print-ebook) 

[![Download Ebook](https://no-cache.hubspot.com/cta/default/4681461/ff6fcba8-6f1c-4535-98a9-4f7644994906.png)](https://cta-redirect.hubspot.com/cta/redirect/4681461/ff6fcba8-6f1c-4535-98a9-4f7644994906)

 Topics: [Build to Print](https://blog.knowlescapacitors.com/blog/tag/build-to-print)

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